The present invention relates to voltage converters, and more particularly DC/DC full bridge converters.
DC/DC converters are electronic devices typically used in power supply applications for personal computers, cell phones, telecommunication equipment, etc. A DC/DC converter receives unregulated DC voltage as input. It outputs regulated DC voltage with a magnitude different than the input DC voltage. A DC/DC converter changes the output voltage magnitude by temporarily converting input DC electrical power to alternate current (AC) electrical power, then the required voltage magnitude can be obtained through a step-up or a step-down operation, finally the AC electrical power is converted back to DC electrical power. DC/DC converters can be built with different types of circuits, including half bridge and full bridge. The topologies of the different types of circuits are well-known.
FIGS. 1A-B illustrates a conventional DC/DC full bridge converter 100. FIG. 1A illustrates a conventional DC/DC full bridge converter 100 during a first operational state. FIG. 1B illustrates a conventional DC/DC full bridge converter 100 during a second operational state.
As illustrated in FIG. 1A, conventional DC/DC full bridge converter 100 includes a primary side 102, a secondary side 104, a transformer 106, a DC input signal provider 108 and a control signal generator 110. Transformer 106 includes a primary side winding 112 and a secondary side winding 114. Primary side 102 includes primary side switches 116, 118, 120 and 122 and primary side winding 112. Secondary side 104 includes secondary side winding 118, an inductor 124, secondary side switches 126 and 128, a capacitor 130 and a resistive load 132.
DC input signal provider 108 is arranged to provide an input signal 134 to primary side 102. Control signal generator 110 is arranged to provide primary side control signals 136, 138, 140 and 142 to primary side switches 116, 118, 120, 122 and secondary side control signals 144 and 146 to secondary side switches 126 and 128, respectively. Primary side winding 112 is connected to primary side switches 116, 118, 120 and 122. Transformer 106 is situated between primary side 102 and secondary side 104. Secondary side winding 114 is connected in series with secondary side switches 126, 128. Inductor 124 is connected to secondary side winding 114. Capacitor 130 is connected in series with inductor 120. Resistive load 132 is connected in parallel to capacitor 130.
DC input signal provider 108 is a voltage source that provides input signal 134. Primary side switches 116, 118, 120 and 122 and secondary side switches 126 and 128 may be any known electrical switching device, non-limiting examples of which include field effect transistors. Transformer 106 is any known system or device that can generate a current from primary side 102 to secondary side 104. Inductor 124 and capacitor 130 together act as a filter for smoothing an output voltage 148 across resistive load 132. Secondary side winding 114 produces a center-tap voltage 150.
Resistive load 132 may be any device or system that is to be driven. Control signal generator 110 is control circuit for supplying pulsed control signals. Primary side control signals 136, 138, 140 and 142 and secondary side control signals 144 and 146 are pulsed control signals generated by control signal generator 110. Primary side control signals 136, 138, 140 and 142 and secondary side control signals 144 and 146 are pulse-width modulated control signals.
In operation through the first and second operational states, conventional DC/DC full bridge converter 100 receives input signal 134 in the form of direct current (DC) as input. Input signal 134 has an associated voltage level that is too high or too low and not suitable to drive resistive load 132. Conventional DC/DC full bridge converter 100 produces output voltage 148, which has a proper voltage level to drive resistive load 132 while maintaining direct current.
During the first operational state as shown in FIG. 1A, control signal generator 110 transmits primary side control signals 136, 142, and secondary side control signal 144 to turn on primary side switches 116, 122, and secondary side switch 126 respectively. At the same time, control signal generator 110 transmits primary side control signals 138, 140, and secondary side control signal 146 to turn off primary side switches 118, 120, and secondary side switch 128 respectively.
The switching on of primary side switches 116 and 122 allows input signal 134 to travel through them as current, thus applying input signal 134 as voltage across primary side winding 112 and inducing a magnetic field 152. Correspondingly, a positive magnetic field 154 is induced in secondary side winding 114. Positive magnetic field 154 generates a current 156 that travels through secondary side switch 126 to produce a first output voltage 158 at the end of the first operational state.
During the second operational state as shown in FIG. 1B, control signal generator 110 transmits primary side control signals 136, 142, and secondary side control signal 144 to turn off primary side switches 116, 122, and secondary side switch 126 respectively. At the same time, control signal generator 110 transmits primary side control signals 138, 140, and secondary side control signal 146 to turn on primary side switches 118, 120, and secondary side switch 128 respectively.
The switching on of primary side switches 118 and 120 allows input signal 134 to travel through them as current, thus applying input signal 134 as voltage across primary side winding 112 and inducing a magnetic field 160 that has an opposite direction as magnetic field 152. Correspondingly, a negative magnetic field 162 is induced in secondary side winding 114. Negative magnetic field 162 generates a current 164 that travels through secondary side switch 128 to produce a second output voltage 166 at the end of the second operational state.
In the end, first output voltage 158 and second output voltage 166 combine to produce output voltage 148. Output voltage 148 has an associated voltage level that is appropriate to drive resistive load 132, but lower than the associated voltage magnitude of input signal 134. This will be further described with additional reference in FIGS. 2-4 below.
FIG. 2 is a timing diagram illustrating the state of primary side control signals 136, 138, 140 and 142 and secondary side control signals 144 and 146 of conventional DC/DC converter 100 during a first and a second operational state.
The figure includes examples of primary side control signals 136, 138, 140 and 142 and secondary side control signals 144 and 146.
Primary side control signal 136 includes a period 202 and a partial period 204. Period 202 includes an on state voltage portion 206 from a time t2 to a time t3 and an off state voltage portion 208 from time t3 to a time t6. Partial period 204 includes an on state voltage portion 210 from time t6 to a time t7 and an off state voltage portion 212 from time t7 forward.
Primary side control signal 138 includes a partial period 214 and a period 216. Partial period 214 includes an on state voltage portion 218 from a time t0 to a time t1 and an off state voltage portion 220 from time t1 to time t4. Period 216 includes an on state voltage portion 222 from time t4 to a time t5 and an off state voltage portion 224 from time t5 to a time tS.
Primary side control signal 142 includes a period 226 and a partial period 228. Period 226 includes an on state voltage portion 230 from time t2 to time t3 and an off state voltage portion 232 from time t3 to time t6. Partial period 228 includes an on state voltage portion 234 from time t6 to time t7 and an off state voltage portion 236 from time t7 forward.
Primary side control signal 140 includes a partial period 238 and a period 240. Partial period 238 includes an on state voltage portion 242 from time t0 to time t1 and an off state voltage portion 244 from time t3 to time t6. Period 240 includes an on state voltage portion 246 from time t4 to time t5 and an off state voltage portion 248 from time t5 to a time tS.
Secondary side control signal 146 includes a partial period 250 and a period 252. Partial period 250 includes an on state voltage portion 254 from time t0 to time t2 and an off state voltage portion 256 from time t2 to time t3. Period 252 includes an on state voltage portion 258 from time t3 to time t6 and an off state voltage portion 260 from time t6 to time t7.
Secondary side control signal 144 includes a partial period 262 and a period 264. Partial period 262 includes an on state voltage portion 266 from time t0 to time t4 and an off state voltage portion 268 from time t4 to time t5. Period 264 includes an on state voltage portion 270 from time t5 to time tS and an off state voltage portion 272 from time tS to a time t9.
In operation, primary side control signals 136, 142, and secondary side control signal 144 have switching frequencies such that primary side switches 116, 122, and secondary side switch 126 are on together. In a non-limiting example, on state voltage portions 206, 230, 266 overlap from time t2 to time t3, similarly, on state voltage portions 210, 234, and 270 overlap from time t6 to time t7. As a result, primary side switches 116, 122, and secondary side switch 126 are on together from time t2 to time t3 and time t6 to time t7.
Primary side control signals 136, 142, and secondary side control signal 144 operate complementarily to primary side control signals 138, 140, and secondary side control signal 146, so that primary side switches 116, 122, and secondary side switch 126 are on while primary side switches 118, 120, and secondary side switch 128 are off, and vice versa. In a non-limiting example, on state voltage portions 206, 230, 266 overlap with off state voltage portions 220, 244, and 256 from time t2 to time t3, thus primary side switches 116, 122, and secondary side switch 126 are on, while primary side switches 118, 120, and secondary side switch 128 are off. From time t4 to time t5, on state voltage portions 222, 246, 258 overlap with off state voltage portions 208, 232, and 268, so that primary side switches 118, 120, and secondary side switch 128 are on, while primary side switches 116, 122, and secondary side switch 126 are off.
A problem associated with conventional DC/DC full bridge converter 100 in FIGS. 1A and 1B is large output voltage overshoot, where there is a huge increase in voltage level of output voltage 148 when input signal 134 is increased rapidly. A large output voltage overshoot causes damages to resistive load 132 or downstream electronic load that is driven by output voltage 148. This will be described in further detail with reference to FIGS. 3 and 4.
FIG. 3 is a timing diagram illustrating an output voltage overshoot scenario of conventional DC/DC converter 100.
The figure includes examples of output voltage 148, input signal 134, and center-tap voltage 150.
Output voltage 148 includes a stable portion 302 from a time T0 to a time T4 and an unstable portion 304 from time T4 forward. Input signal 134 includes a low portion 306 from time T0 to time T4 and a high portion 308 from time T4 forward.
Center-tap voltage 150 includes a pulse 310, a pulse 312, and a pulse 314. Pulse 310 includes an on state voltage portion 316 from a time T1 to a time T2 and an off state voltage portion 318 from time T2 to a time T3, and an amplitude 320. Pulse 312 includes an on state voltage portion 322 from time T3 to a time t5 and an off state voltage portion 324 from time T5 to a time T6, and an amplitude 326. Amplitude 326 includes amplitude 320 and an increased portion 328. Pulse 314 includes an on state voltage portion 330 from time T6 to a time T7, off state voltage portion 332 from time T7 to a time TS, and amplitude 326.
In operation, when input signal 134 experiences a rapid increase in voltage level, it transitions from low portion 306 to high portion 308 at time T4. As a result, output voltage 148 will experience an overshoot in voltage level as shown by the change in the flat line with a zero slope in stable portion 302 to the straight line with a positive slope in unstable portion 304. Center-tap voltage 150 will also experience an increase in voltage level. Prior to time T4, the voltage level of center-tap voltage 150 is represented by amplitude 320 of pulse 310. At time T4, the voltage level of center-tap voltage 150 is increased by an amount equal to increased portion 328, so that amplitude 326 of pulse 312 is equal to the sum of amplitude 320 and increased portion 328. From time T4 forward, center-tap voltage 150 has voltage level equal to amplitude 326, as shown in pulses 312 and 314.
As noted in FIG. 3, input signal 134 has a rapid increase in voltage level when transitioning from low portion 306 to high portion 308 at time T4, a goal of conventional DC/DC converter 100 is to maintain a constant output voltage 148 in the face of changing input signal 134. However, as noted in FIG. 3, as a result of the rapid increase in voltage level of input signal 134 at time T4, output voltage 148 is increased as noted by unstable portion 304. This increase may negatively affect, or worse damage, resistive load 132 that is to be driven by output voltage 148. The instability, as noted by unstable portion 304, is directly caused by the overshoot of a increase voltage in the DC-AC-DC conversion within conventional DC/DC converter 100. This will be further described with reference to FIG. 4.
FIG. 4 is a wave diagram illustrating an output voltage overshoot scenario an output voltage overshoot scenario of conventional DC/DC converter 100;
The figure includes examples of input signal 134 and output voltage 148.
Input signal 134 includes a low portion 402 from a time a to a time b, a surge portion 404 from time b to a time c, and a high portion 406 from time c forward. Output voltage includes a low portion 408 from time a to time b, an overshoot portion 410 from time b to a time d and a recovery portion 412 from time d forward.
In a non-limiting example, input signal 134 has a voltage value of 44 volts in low portion 402 and output voltage 148 has a voltage value of 12 volts in low portion 408. When input signal 134 increases rapidly from 44 volts in low portion 402 to 56 volts in high portion 406 through surge portion 404, output voltage 148 experiences an overshoot of 2.32 volts in overshoot portion 410 from time b to time d, then gradually decreases back to 12 volts in recovery portion 412 from time d forward. The voltage overshoot of 2.32 volts experienced by output voltage 148 causes damages or malfunctions to electrical equipments connected to output voltage 148.
What is needed is a DC/DC full bridge converter that reduces the output voltage overshoot when input voltage is increased rapidly.